ASIC design, EDA Solutions, Europractice

EDA Solutions and Europractice to host mixed-signal ASIC design training seminars at DATE 2008

News Release from: EDA Solutions Limited
14/02/2008

EDA Solutions and the Fraunhofer Institute, one of the Europractice Support Centres, will co-host a program of training seminars on Europractice design kits for the latest version of Tanner Tools at DATE 2008. The practical training sessions, to be held on Wednesday 12 March 2008, will give a hands-on introduction to the design kits and Tanner Tools Pro. They are free of charge and open to all those with an interest in analog and mixed-signal ASIC design.

The Europractice IC service offers low-cost ASIC prototyping and small volume production through its multi-project wafer (MPW) service and dedicated wafer runs. MPW allows system-on-chip designers to obtain samples or small production quantities of digital or mixed-signal devices at less than 10% of the cost of using a dedicated production run; sharing masks and wafers with other chip designs achieves this.

Design kits for Euopractice’s MPW service have been developed by the Fraunhofer Institute and use the latest version of Tanner EDA’s Windows-based tool suite for analog and mixed-signal IC and MEMS design, Tanner Tools 13.0. Tanner Tools consists of S-Edit for schematic capture, T-Spice for simulation, L-Edit for layout and HiPer Verify for design verification. The latest upgrade adds Verilog-A model support to T-Spice. L-Edit is boosted with better library support, improvements in schematic driven layout (SDL) and a new SDL automatic router. HiPer Verify gets a hierarchical, foundry-compatible netlist extraction tool – HiPer Extract. Finally, Tanner has introduced HiPer PX, a 3D extraction tool for accurate extraction of interconnect and substrate parasitics. These significant upgrades will also be demonstrated on the EDA Solutions stand during the show.

EDA Solutions will also be promoting new additions to the processes available through MOSIS’ MPW service at DATE. MOSIS has added protoype and low volume fabrication access to IBM’s 8WL (130nm) and 6WL (0.25 micron) SiGe BiCMOS technologies, as well as IBM’s latest 65nm and image sensing technology (CIMG) processes.