Synplicity and Actel, Synplify
Synplicity and Actel extend their helping hand to FPGA designers
News Release from:
Actel Europe Ltd
02/05/2006
Synplicity and Actel Corporation today announced that the companies
have expanded their OEM agreement. Under the terms of the
multi-year agreement, Actel obtains the right to distribute the Synplify
Pro, Identify and Synplify DSP software solutions to its customers as
part of its Libero Integrated Design Environment. The expanded
agreement will also provide Actel customers with future access to
Synplicity¹s physical synthesis technology.
This expanded OEM agreement leverages the strengths of each company to
improve the FPGA designer¹s experience. Focusing on
delivering innovative single-chip FPGA solutions, Actel has a long-term
strategy of teaming with leading software tools vendors to provide a
best-in-class design environment. Actel and Synplicity have worked closely
to integrate Synplicity¹s tools into the Libero IDE. Actel is the only FPGA
vendor to distribute the industry-leading Synplify Pro software, providing
Libero Platinum users with improved quality of results (QoR) and advanced
implementation features.
This agreement also bolsters Actel¹s hardware debugging capabilities by
adding the Identify RTL debugger to the Gold and Platinum versions of the
Libero IDE. The Identify product is a debug-centric verification tool that
offers the fastest method of finding errors in a design by providing
simulator-like visibility into a live, running FPGA. The Identify RTL
Debugger is the first tool to allow designers to instrument and debug
directly in RTL source code.
For designers of DSP systems, the addition of Synplicity's Synplify DSP
software to the Libero IDE enables a seamless flow from The Mathworks¹
Simulink design environment to RTL design. Synplify DSP software uniquely
uses proprietary system-level synthesis algorithms to automatically generate
highly optimized RTL code ready for logic synthesis, eliminating prior
hand-coded, error-prone and time-consuming methodologies requiring numerous
iterations between the DSP algorithm architect and the RTL hardware
designer.
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